Recent developments in memory applications, such as mass storage, code memory, and other multimedia applications increasingly require memory devices with higher density. Mass storage applications may include memory cards (for example, for mobile computers), solid-state memory (for example, sturdy and/or reliable storage disks), digital cameras (for recording still or moving images and sound), and voice or audio recorders for recording near CD quality sound).
Code memory applications may include basic input/output systems (BIOS) or network applications (for example, memory in a personal computer, other terminal, router, or hub), telecommunications applications (for example, switches), mobile phone applications (for example, codes and/or data), and other electronic handheld information device applications (for example, codes and/or data for personal digital assistants (PDA), palm operating systems (POS), or personal communications assistants (PCA)).
Generally, mass storage applications use memory that is lower cost, higher density, and/or has better program/erase (P/E) cycling endurance, while code memory applications have faster random access and/or are executable in place (XIP).
Related art memories may include dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory (NVM). Non-volatile memory may include mask read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory (for example, flash erase EEPROM), and ferro-electric memory. Non-volatile memory does not lose data when power is lost, but generally does not permit random access and is generally slower than volatile memory.
Flash memory may be formed by a combination of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). Flash memory may be NAND or NOR flash memory. Erase and program operations may be performed in a flash memory by the application of different voltages to each flash memory cell.
Generally, NAND flash memory is more conducive to mass storage applications due to smaller cell size, higher density, lower power and/or better endurance, while NOR flash memory is more conducive to code storage applications due to larger cell current and/or faster random access.
NAND flash memory may include a string of serially connected cells (for example, 16 cells may make up a string). The string may include one or mroe string select transistors. NAND flash memory may have a relatively small “on” cell current and hence, relatively slow sensing time (for example, 5-10 ms). NAND flash memory may perform a read operation by simultaneously sensing and latching a page unit (for example, 512 bytes) to page buffers. NAND flash memory may read data from page buffers latch at a relatively high speed (for example, 50 ns).
NAND flash memory may perform program and/or erase operations by tunneling (for example, Fowler-Nordheim (F-N) tunneling). A program operation may include a relatively fast serial data loading to page buffers (for example, 50 ns), where cells (for example, 512 bytes) are simultaneously programmed. An erase operation may be a block unit erase where a number of pages (for example, 32 pages of 16K bytes cells) are simultaneously erased.
Reliable F-N tunneling may be performed at approximately 10 mV/cm. which may result in lower power consumption, lower temperature dependence, more uniform program/erase operation, and/or easier device/voltage scaling.
NAND flash program operation may utilize a coupling between a gate and a channel. For example, a programmed cell may have a larger difference between the gate and the channel than an unprogrammed cell. NAND flash program operation also may also utilize a threshold voltage distribution, an example of which is shown in FIG. 1. FIG. 1 illustrates the relationship between a word line voltage Vword line, a read voltage Vread, and a cell voltage distribution Vth of an unprogrammed (or erased) cell and a programmed cell.
NAND flash memories may include page buffers for facilitating data transfers into and out of a NAND flash cell array. Page buffers generally may perform two functions, sensing and latching. An example of a related art page buffer is illustrated in FIG. 2. As shown, the example, related art page buffer may include a switching transistor, a load transistor for enabling a load current to flow to permit sensing, and a latch for latching the sense data, triggered by a latching enable signal.
FIGS. 3a and 3b illustrate an example, related art page buffer and an example of a read operation of the example, related art page buffer. As shown in FIG. 3b, the example, related art page buffer may operate in several periods, including a bit line (B/L) discharge period, a bit line (B/L) precharge period, a develop period, a sensing and latch period, and a reset (or recovery period).
FIGS. 4a and 4b illustrate another example, related art page buffer and another example of a read operation of the example, related art page buffer. As shown in FIG. 4b, the example, related art page buffer may also operate in several periods, including a bit line (B/L) discharge and page buffer reset period, a sensing period, a latch and data out period, and a reset (or recovery period).
FIGS. 5a and 5b illustrate yet another example, related art page buffer and yet another example of a read operation of the example, related art page buffer. As shown in FIG. 5b, the example, related art page buffer may also operate in several periods, including a page buffer reset and bit line (B/L) discharge period, a bit line (B/L) precharge period, a sensing period, a data latch period, a reset (or recovery period), and a data out period.
FIG. 6 illustrates the structure of an example, related art page buffer in more detail. As shown, the page buffer of FIG. 6 includes a precharge block, a bit line (B/L) selecting and bias block, a first and second latch and sense block, and a column gate circuit.
The page buffers of FIGS. 5a-6 may perform interleave operations, but also may be relatively complex structurally, have a relatively large layout area, and/or be relatively slow.